Scheduling Blocks for Hierarchical Compiled Simulation
نویسنده
چکیده
Although preserving the hierarchy in compiled simulation can significantly reduce the compilation time for the code generated by the circuit compiler, the possibility of introducing pseudo-cycles due to element grouping can impair the performance of the generated code. A new approach to this problem is presented which uses dependency information to reduce the number of times a particular block must be simulated. The problem of determining the minimum schedule is shown to be NP-Complete, and a set of heuristics for the problem is presented. Experimental results for different combinations of these heuristics are presented. An algorithm for determining dependency information from the contents of a block is presented along with a new approach that can be used when the content of one or more blocks is unknown. SCHEDULING BLOCKS FOR HIERARCHICAL COMPILED SIMULATION Peter M. Maurer Department of Computer Science and Engineering University of South Florida Tampa, FL 33620
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تاریخ انتشار 1996